| 摘要 |
PROBLEM TO BE SOLVED: To remarkably reduce the wiring resistance of a semiconductor storage device without increasing the memory map area, by widening the width of a signal line for transmitting the signal/voltage related to memory cell line selecting operations in an area adjacent to the second portion of row selecting lines having structure. SOLUTION: Conductive wiring which becomes main word lines contains a conductive line 10a linearly extended in the direction of rows and conductive lines 10b which are laid near the peripheries of memory arrays MA and have an intensive structure in which the positions of the lines 10b on the array MA are shifted in the direction of columns. The intensive structure contains a second portion in which a first portion is shifted in the direction of columns. In the area between the memory arrays MA adjacent to each other in the direction of columns, namely, in sense amplifier zones SB #a and #b, a signal line for transmitting the instruction signal of a bit-line equalizer and a cell plate line for transmitting cell plate voltages are laid in the same layer as that of the conductive lines 10a and 10b of the main word lines and the width of an objective line of the signal and cell plate lines is widened across a vacant area 15. |
