发明名称 |
High performance superscalar alignment unit |
摘要 |
An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line. The issue position or positions to which an instruction may be dispatched is limited depending upon the position of the instruction's start byte within a line. By limiting the number of issue positions to which a given instruction within a line may be dispatched the number of cascaded levels of logic required to implement the instruction alignment unit may be advantageously reduced.
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申请公布号 |
US6006324(A) |
申请公布日期 |
1999.12.21 |
申请号 |
US19980182973 |
申请日期 |
1998.10.29 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
TRAN, THANG;WITT, DAVID B. |
分类号 |
G06F9/30;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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