| 摘要 |
A frequency synthesizer for generating two or more output frequency ranges using a Phase Locked Loop (PLL) circuit having a single voltage-controlled oscillator (VCO). In a first embodiment, a frequency multiplier is connected to the output of the VCO. The output of the VCO and the output of the frequency multiplier are selectably fed back, depending upon which output frequency is desired. The output frequency may be taken directly from the VCO or the frequency multiplier. When the output frequency is taken from the output of the frequency multiplier, a control signal adjusts the gain of the phase detector and/or loop filter in order to compensate for the loop gain caused by the frequency multiplier. In a second embodiment, instead of adjusting the phase detector and/or loop filter gain, the values of the N and M dividers are adjusted. In a third embodiment, a frequency multiplier is connected to the output of the VCO and multiplies the output by a predetermined multiplier value. The N divider value is adjusted by a control signal, such that when the output is taken from the frequency multiplier, the ratio N/M is set equal to the predetermined multiplier value. In a fourth embodiment, the M value, the N value, the phase detector gain and the loop filter gain may all be adjusted in the circuit of the third embodiment, in order to keep the N/M ratio equal to the multiplier "H," and to compensate for the loop gain caused by changing the value of M. The technique described herein is useful for generating constant amplitude phase or frequency modulated signals like the radio signals defined for the GSM or DCS 1800 bands.
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