发明名称 |
Static memory with low power write port |
摘要 |
The write port circuits of a static memory cell includes a first conditional conduction path between a first output of the latch and ground active if and only if both a word line input and a write data true bit line input receive active signals. The write port circuit includes a second conditional conduction path between a second output of the latch and ground active if and only if both the word line and a write data complement bit line receive active signals. The first and second conditional conduction paths may be formed by a series connection of the source-drain paths of two transistors. In each conditional conduction path the gate of a first transistor receives a corresponding column signal and the gate of a second transistor is connected to the word line. The first and second transistors for each conduction path may be N-channel MOS transistors formed in a single N-type region. The first and second transistors forming the conditional conduction paths may be in either order. The word line transistors may bee shared between bit line transistors of a single memory cell or of memory cells in plural contiguous adjacent columns. The memory cells may include a plurality of write ports with this inventive write port circuit used for each write port.
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申请公布号 |
US6005794(A) |
申请公布日期 |
1999.12.21 |
申请号 |
US19980106034 |
申请日期 |
1998.06.26 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SHEFFIELD, BRYAN D.;JAMISON, GEORGE B.;SPRIGGS, STEPHEN WAYNE |
分类号 |
G11C8/16;G11C11/419;(IPC1-7):G11C11/00 |
主分类号 |
G11C8/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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