METHOD FOR TEST ABILITY ANALYSIS AND TEST POINT INSERTION AT THE RT-LEVEL OF A HARDWARE DEVELOPMENT LANGUAGE (HDL) SPECIFICATION

摘要

A method of producing a synthesizable RT-Level VHDL specification for input to a synthesis tool to generate a gate-level circuit having testability enhancement, the method comprising the steps of developing a synthesizable RT-Level VHDL specification representative of said circuit, analyzing said VHDL specification to produce a VHDL Intermediate Format (VIF) representation; transforming said VIF representation into a Directed Acyclic Graph (DAG); performing testability analysis on said Directed Acyclic Graph by computing and propagating Testability Measures (TMs) forward and backward through VHDL statements of said Directed Acyclic Graph; identifying the bits of each signals/variables on which faults are hard to detect; and performing test point insertion in said specification at the RT-Level by adding new VHDL test statements to improve testability.