Testing field programmable gate array with multi-programmable intermediate connections

摘要

The method of testing of FPGA is carried out with the selection of test configurations, which facilitate a large as possible identical programming of the macro-cells (A,B). A multiple of the lines of the memory matrix, which correspond to the macro-cells (A,B) of a test configuration, are simultaneously programmed and deleted. A multiple of lines of the memory matrix are simultaneously programmed inside a macro-cell line.