| 摘要 |
PROBLEM TO BE SOLVED: To obtain a testing apparatus which prevents the occurrence of a timing error by a method wherein scan data according to a test pattern is written into a memory through a first scan chain and the scan data is read out from the memory through a second scan chain which couples a plurality of unit memory circuits constituting the output circuit of the memory. SOLUTION: When a test mode is selected at the high level '1' of a selector signal from a pin 62, respective selectors in multiplexers 78 to 81, a multiplexer 96 and scan flip-flops 84, 86 select input terminals for a test mode. Signals which are input from pins 63, 64 are supplied to data terminals of flip-flops 90, 91 via the multiplexers 79, 80, and the address '0' of a memory 88 is designated. A scan clock is supplied sequentially to scan flop-flops 92 to 94 on the output side, and the same sequence is repeated with reference to all addresses of the memory 88. |
