发明名称 PLL CONTROL METHOD FOR DATA RECEIVER
摘要 PROBLEM TO BE SOLVED: To synchronize a phase at the time of pulling in regardless of a line characteristics with respect to the PLL control method to control a phase of a phase locked loop PLL in order to take synchronization of a received signal by the data receiver. SOLUTION: The PLL control method has a step where a timing phase of a PLL is locked in response to a training signal, a step where a right side reference value is obtained from a sum of tap coefficients of a right side tap with respect to a center tap of an automatic equalization section 5 and a left side reference value is obtained from a sum of tap coefficients of a left side tap with respect to the center tap of the automatic equalization section 5 just after locking, a step where a 1st difference between the sum and the right side reference value is obtained after calculating the sum of the tap coefficients of the right side tap with respect to the center tap of the automatic equalization section 5 and a 2nd difference between the sum and the left side reference value is obtained after calculating the sum of the tap coefficients of the left side tap with respect to the center tap of the automatic equalization section 5, and a step where a difference between the 1st difference and the 2nd difference is obtained to get a control signal for the PLL.
申请公布号 JPH11340960(A) 申请公布日期 1999.12.10
申请号 JP19980147354 申请日期 1998.05.28
申请人 FUJITSU LTD 发明人 OKITA RYOJI
分类号 H03L7/08;H03L7/06;H04B3/10;H04L7/02;H04L7/033;H04L27/22;H04L27/38 主分类号 H03L7/08
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