发明名称 |
Data conversion interface for selecting bit length of serial-parallel or parallel-serial converted data |
摘要 |
The data conversion interface has a clock signal generator (20) which produces a clock signal in response to a mode signal indicative of operation in one of at least two data length modes of transmission. A serial/parallel converter (38) receives the clock signal, the mode signal and serial data, and converts the serial data into parallel data with a data length defined by the mode signal. The data lengths may be 8 bit and 16 bit. An Independent claim is included for a data conversion interface.
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申请公布号 |
DE19900151(A1) |
申请公布日期 |
1999.12.09 |
申请号 |
DE19991000151 |
申请日期 |
1999.01.05 |
申请人 |
LG SEMICON CO. LTD., CHEONGJU |
发明人 |
YANG, YIL-SUK |
分类号 |
H03M9/00;(IPC1-7):H03M9/00;H03K19/017 |
主分类号 |
H03M9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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