| 摘要 |
A tunable digital oscillator circuit comprising a first dual-clock pulse generator (202), a second dual-clock pulse generator (204), a run controller (104), a stop controller (106) and a decoder (108). The first and second dual-clock pulse generators are coupled in a cascaded manner with the output of the first dual-clock pulse generator provided as an input to the second dual-clock pulse generator. Each of the first and second dual-clock pulse generators is preferably tunable, in that, they can output one clock signal from a predetermined number of frequencies. The run controller is preferably coupled to receive a start signal and the output of the second dual-clock pulse generator. The run controller provides the input to begin and maintain the first and second dual-clock pulse generators in the state of generating a clock signal. The stop controller is coupled to receive a clock signal from the first dual-clock pulse generator, and a stop signal. The tunable digital oscillator circuit can start or stop the clock within two clock cycles. The decoder receives a period select signal and provides a control signal to the first and second dual-clock pulse generators to select one of a predetermined number of frequencies for the clock signal.
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