| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for manufacturing a DRAM cell capacitor by which misalignment between storage electrode contact holes and storage electrodes is prevented. SOLUTION: A first insulating layer 108 including bit lines 110, a second insulating layer 116, a first material layer 118 and a second substance layer 122 on the second insulating layer 116 through a third insulating layer 120 are formed in sequence. A storage electrode forming region is determined on the second material layer 122 to form a mask pattern 124. A second substance layer 122, the third insulating layer 120, the first material layer 118, the second insulating layer 116 and the first insulating layer 108 are etched in sequence through the use of the mask pattern 124 to form contact holes 125. After filling the contact holes 125 with conductive layers, the second material layer 122 including the conductive layers is etched for flattening in such a manner that the surface of the third insulating layer 120 is exposed. The third insulating layer 120 is eliminated using the first material layer 118 as etching stopping layer to form storage electrodes. |
