DELAY GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING SAME

摘要

PROBLEM TO BE SOLVED: To provide the delay generating circuit which can easily obtain a desired delay time and easily adjust the delay time, and facilitates debugging and correction to shorten TAT after the correction and the semiconductor integrated circuit device using the delay generating circuit. SOLUTION: This is a delay generating circuit in which plural basic circuits are arranged and which generates a desired clock signal and a basic circuit consists of a combination of five inverters INV1 to INV5 and has an input terminal 11, an output circuit O1 for basic circuit connection, and output terminals O2 and O3 exclusively for delay output; and output is obtained from the output terminals O2 and O3 of a basic circuit by which a desired delay time can be obtained and this obtained signal is used to generate the desired clock signal. Relating to the layout pattern of the cell of this basic circuit, the input terminal I1 and output terminals O1 to O3 are formed in structure which can be connected only by the top wiring layer of a manufacture process and cells are connected by only one layer of the top wiring layer.