| 发明名称 |
Memory transactions on a low pin count bus |
| 摘要 |
A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.
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| 申请公布号 |
US5991841(A) |
申请公布日期 |
1999.11.23 |
| 申请号 |
US19970936848 |
申请日期 |
1997.09.24 |
| 申请人 |
INTEL CORPORATION |
发明人 |
GAFKEN, ANDREW H.;BENNETT, JOSEPH A.;POISNER, DAVID I. |
| 分类号 |
G06F13/10;G06F12/00;G06F13/16;G06F13/42;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/10 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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