发明名称 Dual-ported memory controller which maintains cache coherency using a memory line status table
摘要 A symmetric multiprocessor system constructed from industry standard commodity components together with an advanced dual-ported memory controller. The multiprocessor system comprises a processor bus; up to four Intel Pentium TM Pro processors connected to the processor bus; an I/O bus; a system memory; and a dual-ported memory controller connected to the system memory, the dual ported memory controller having a first port connected to the processor bus to manage processor to system memory transactions and a second port connected to the I/O bus to manage I/O transactions. Furthermore, two such systems can be connected together through a common I/O bus, thereby creating an eight-processor Pentium TM Pro processor SMP system.
申请公布号 US5991819(A) 申请公布日期 1999.11.23
申请号 US19960760126 申请日期 1996.12.03
申请人 INTEL CORPORATION 发明人 YOUNG, GENE F.
分类号 G06F13/16;(IPC1-7):G06F13/00 主分类号 G06F13/16
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