发明名称 |
PRIORITY SELECTING CIRCUIT |
摘要 |
PURPOSE:To constitute a circuit with a small number of ICs and a small amount of delay time regardless of an increment of the number of process request sources, by storing previously the priority selection logic in a memory. CONSTITUTION:A storage element 60 is provided to supply a process request given from each of process request sources A0-A3 in correspondence to each bit of the address, and only one of the supplied and activated address bits is written previously into the element 60 to be delivered as a data. For instance, a prescribed priority selection logic having a contents shown by a table (priority: A0>A1>A2>A3) is written previously into a ROM60 having a capacity of 16 words by 4 bits. Then the request sources A0-A3 are connected to address inputs RA0-RA3 respectively, and the results of selection based on a prescribed logic are delivered to priority selection result display devices B0-B3 from data outputs D0-D3. |
申请公布号 |
JPS576925(A) |
申请公布日期 |
1982.01.13 |
申请号 |
JP19800080197 |
申请日期 |
1980.06.16 |
申请人 |
HITACHI LTD;NIPPON TELEGRAPH & TELEPHONE |
发明人 |
SHIYOUDA AKIO;MIKI SHIYUUJI |
分类号 |
G06F9/48;G06F13/18;G06F13/362 |
主分类号 |
G06F9/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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