| 摘要 |
PROBLEM TO BE SOLVED: To generate the inspection pattern of a semiconductor integrated circuit for operating the inspection of a response at an actual operating speed even when the design of a semiconductor integrated circuit in which a timing is considered only for a path to be used in an actual operation. SOLUTION: The timing analysis of a semiconductor integrated circuit to be inspected is operated by a timing analysis processing (ST100), and an error path in which a timing error is generated in an actual operating speed is detected. The candidates of a partial inspection pattern are successively selected by a partial inspection pattern candidate selection processing (ST102) so that arbitrary failure (for example, degenerate failure) selected by a failure selection processing (ST101) can be inspected. When an inspection pattern generated by all the selected partial inspection pattern candidates activates the error path in a path activation inspection processing (ST103), the error path is back tracked so that an another inspection pattern can be generated by an another candidate selection processing (ST104). |
