发明名称 |
DECODER |
摘要 |
PROBLEM TO BE SOLVED: To enable a decoder to conduct decoding accurately based on a common STC between a processor and an image decode means while the decoding of a transport stream is conducted on the processor and the reproducing of the STC is stably conducted. SOLUTION: The capacity of a 2nd buffer means 24 is set to be the capacity that absorbs dispersion in an arrival time due to arbitration and can conduct the supply of a packet to a processor 13 stably. Furthermore, this decoder is provided with a master clock generating circuit as a time reference and an STC is handed in a form of a difference between a master clock and a PCR to conduct the reproducing of the STC. Furthermore, a PCR input to an STC reproducing means is delayed by a delay time when the packet reaches the processor 13. |
申请公布号 |
JPH11313314(A) |
申请公布日期 |
1999.11.09 |
申请号 |
JP19980116761 |
申请日期 |
1998.04.27 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
SHIMAZAKI HIROAKI;KOMENO JUNICHI;UENO TAKAFUMI |
分类号 |
H04N19/423;H04N7/08;H04N7/24;H04N19/00;H04N19/44;H04N19/70 |
主分类号 |
H04N19/423 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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