SYNCHRONIZATION DEVICE AND ITS METHOD

摘要

PROBLEM TO BE SOLVED: To prevent remarkable deterioration in an error rate by preventing synchronization in a timing deviated by a symbol period/2 from an optimum identification point that is a peak point of a sine wave of Ich and Qch signals. SOLUTION: A memory circuit 105 generates an envelope signal from Ich and Qch signals from received Ich and Qch signals after sampling based on a recovered clock of a prescribed sampling period, and when a discrimination device 110 discriminates it that a difference of sampling result between an even number and an odd number of the envelope signals exceeds a threshold level 131, a controller 111 varies a phase of a recovered clock in a synchronization timing to minimize the difference, and when a discrimination device 115 discriminates that the phase difference is inverted, the recovered clock from the controller 111 is delayed by a delay device 118 to be synchronously with the input Ich and Qch signals to prevent remarkable deterioration in the error rate.