发明名称 Double inlay process for forming interconnections especially in multi-level ICs
摘要 A double inlay process for forming interconnections employs a single photolithography and etching operation to form aligned openings (59, 64) through two oxide layers (56,60) to a conductive layer (54). A double inlay process for forming interconnections comprises: (a) forming a first oxide layer (56) over a substrate (50) bearing first conductive layers (53,54) such that the oxide layer has high and low raised regions (57) above the conductive layer locations; (b) forming a conformal insulation layer (58) above the oxide layer; (c) removing the insulation layer above the highest raised region to form a first opening (59) which exposes part of the oxide layer; (d) forming a second oxide layer (60) on the insulation layer; (e) patterning the second and first oxide layers to form a second opening (64) which exposes the first opening and one (54) of the conductive layers; and (f) forming a second conductive layer (68) which fills the openings to form a connection with the exposed first conductive layer.
申请公布号 FR2778268(A1) 申请公布日期 1999.11.05
申请号 FR19980010540 申请日期 1998.08.19
申请人 UNITED MICROELECTRONICS CORPORATION 发明人 TSAI MENG JIN
分类号 H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/28 主分类号 H01L21/768
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