| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit, capable of autonomously switching plural voltage controlled oscillators and switching the frequency division ratio of an oscillation clock corresponding to the frequency of a reference clock. SOLUTION: In this PLL circuit 10 of constitution loaded with the three voltage-controlled oscillators 25-1, 25-2 and 25-3 provided with different oscillation frequency bands for appropriately switching them corresponding to the frequency of the reference clock RCK, when UP signals/DOWN signals exceeding a certain fixed width are outputted from a frequency phase comparator 21, it is detected that phases do not match by an error detection circuit 31 and error signals are outputted over more than the time of one cycle of a frequency division clock VCK in a stretcher circuit 32. Also, in the output period of the error signals, pulse clocks, NEXT are counted in a counter circuit 33 and the counted value is used as the changeover signal of a selector 26. |
