| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase difference restoring circuit and a phase difference restoring method. SOLUTION: This phase difference restoring circuit 11 generates two output signals RCLK and MCLK2 in synchronism with reference clock signals Rxclk. The RCLK is a signal for receiving the data of an input pipeline 15 and synchronizing the operation of interface logic 13. The MCLK2 is a signal provided with the same phase as that of the RCLK and is obtained by delaying the MCLK1 generated by a delay-locked loop RDLL 17 dedicated to input in a delay part 19. The MCLK2 is operated, in response to the reference clock signals Rxclk, not only in the active mode but also in the standby mode and synchronizes the input pipeline 15. The MCLK2 is fed back to the RDLL 17 and used as the locking reference signal of the RDLL 17. The delay part 19 is provided for example, with a delay time which is adjustable on the outside and the delay part 19 is provided with an RC delay part controlled by a laser fuse or on the outside. Thus, the phase difference in the internal signals generated in synchronism with external clock signals is adjusted from the outside or in the inside. |
