| 摘要 |
A direct digital frequency synthesizer featuring an accumulator having a modulo overflow signal addressing a multiplexer. The multiplexer receives a series of delay signals generated from digital circuits. The delay signals establish the phase of a reference oscillator. The number of units of delay are sufficient to resolve expected jitter. The accumulator is a digital counter which increments by only a single digit for each count, such as a Gray code counter. In one embodiment, the delay signals are generated by a charge pump feeding individual logic circuits driving integrated capacitors in a loop. Feedback to the charge pump establishes that the total delay will subdivide a single clock cycle of the reference clock. In a second embodiment, a single shifter or several shifters, with output in phase reversal relation, subdivide a single clock cycle. A clock multiplier and divider are used to assure the synchronism of each clock cycle with the total number of units of delay. The output of the multiplexer is the reference oscillator signal, adjusted by the phase delay, forming a synthesized output frequency.
|
