发明名称 |
Semiconductor memory device |
摘要 |
An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.
|
申请公布号 |
US4689770(A) |
申请公布日期 |
1987.08.25 |
申请号 |
US19850792071 |
申请日期 |
1985.10.28 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MIYAMOTO, HIROSHI;MASHIKO, KOICHIRO;KOBAYASHI, TOSHIFUMI;YAMADA, MICHIHIRO |
分类号 |
G11C11/401;G11C5/02;G11C7/18;G11C11/4097;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):G11C11/24 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|