发明名称 Signal processor
摘要 Decoders A and B decode MPEG-2 bitstreams A0 and B0 and re-encoders 8 and 10 re-encode them as bitstreams AI and BI comprising only I frames. A switch (S1) switches from recoded stream AI to recoded stream BI to achieve a splice AI/BI. The spliced bitstream is stored in an I-frame store (12). The stored bitstream AI/BI is re-encoded in an encoder 4. A new transitional GOP is defined beginning at the splice. The new GOP is defined by picture type decision rules which may change the length of the transitional GOP compared to the GOPs of streams A and B. The transitional GOP provides a prediction of the position in stream B where the occupancy value of stream C should coincide with that of B. A target for the new number of bits in the new GOP is calculated dependent on the difference between the occupancy value of stream C at the splice and a prediction of the occupancy of stream B at the predicted position. The occupancy value of stream C is controlled in accordance with the target so that it tends towards the occupancy value of stream B at the predicted position. In another version, the target is updated at regular intervals throughout the GOP, and the change allowed is limited. <IMAGE>
申请公布号 GB9920276(D0) 申请公布日期 1999.10.27
申请号 GB19990020276 申请日期 1999.08.26
申请人 SONY UNITED KINGDOM LIMITED 发明人
分类号 H04N5/91;G06T9/00;H04N5/92;H04N7/24;H04N7/26;H04N7/50 主分类号 H04N5/91
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