| 摘要 |
An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a delay locked loop, for converting the LVDS clock signal into a full-swing clock signal and generating a plurality of clock recovery signals from the converted full-swing clock signal, and a plurality of data recovery signals from the converted full-swing clock signal, and a plurality of data recovery channels, each channel coupled to a data signal and comprising an LVDS converter, a skew adjust circuit, a sampler array, a phase adjusting circuit. The delay locked loop and the data channel circuitry combine to remove skew from LVDS signals by generating multiple clock signals, sampling the data at multiple intervals, using the samples to eliminate skew, and retrieving correct data samples from the data signals. In another embodiment, the sampler array comprises a plurality of transition sampling circuits, for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sample data signal responsive to the sampled transition, and a plurality of center sampling circuits, for sampling a center position of each serial bit of data and generating a center sample signal responsive to the sample, and the phase adjusting circuit generating skew control signals responsive to the center sample signals, lock signals, and transition data signals received from the sampler array. |
