| 摘要 |
<p>A memory array has a floating gate transistor cell (120) connected to a bit line (122) and a bit line driver circuit comprising a variable impedance FET (125) and an active load (311,311) powering the bit line from a supply node (123). A control circuit (126,302,304) selects a voltage applied to the gate of the variable impedance FET (125) to control the bit line voltage, eg, in dependence on parameters of the cell (120). <MATH></p> |
