发明名称 Method of fabricating a microelectronic package having polymer ESD protection
摘要 A semiconductor package having positioned therein a protection layer which protects the integrated circuit chip from electrostatic discharge (ESD) damage. The protection layer is made of a material that has at steady state a high electrical resistance, but when a high ESD potential is applied to it, it becomes highly conductive. A preferred material is SurgX TM , which is a polymer. The layer is positioned to shunt the potential away from the chip, and can be positioned operatively between a signal lead and a power plane or between different signal leads. That is, the protection layer can be sandwiched between the lead and the conductive member, or the lead can be within the layer. Another preferred construction incorporates the protection material in a tape construction as a thin layer sandwiched between and bonded to a layer of leads and a ground plane.
申请公布号 US5970321(A) 申请公布日期 1999.10.19
申请号 US19970936829 申请日期 1997.09.25
申请人 LSI LOGIC CORPORATION 发明人 HIVELY, JAMES W.
分类号 H01L27/04;H01L21/56;H01L21/60;H01L21/822;H01L23/31;H01L23/60;H01L23/62;H01L29/74;(IPC1-7):H01L21/60 主分类号 H01L27/04
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