| 摘要 |
A flash EEPROM includes a an array of nonvolatile memory cells each having a cell transistor of a double gate structure and a program area for the floating gate of the cell transistor. The flash EEPROM is subjected to programming, flash erasing and read mode, each of a byte by byte mode. The flash EEPROM includes first through third selection transistors, for disconnecting the source, drain and control gate of the selected cell transistor from those of the unselected cell transistors in a byte for suppressing a disturbance between cell transistors.
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