Digital signal processor architecture optimized for memory accesses

摘要

Two memory access modules (10) and an arithmetic module (12) are connected to a memory address bus (16) and are controlled by a connection manager module (14). The memory access modules (10) contain read/write addresses (STAQ), and the arithmetic module (12) contains read/write data (LDDQ, STDQ). Data and addresses may not arrive in the files simultaneously, and the memory modules execute an access instruction every cycle