| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the variations in time delay or aging effect for control using the number of pulse transmissions, by forming a logical delay circuit which takes a pulse motor controlling pulse as a clock, using a logic such as a counter and a shift register, thereby delaying a limiting signal. SOLUTION: This control circuit 1 is constituted of a control circuit 2, a drive circuit 3, a transmitting circuit 4, a delay circuit 5, a CW input 6, a CCW input 7, and gate logics 8, 9. When a mechanism with a pulse motor 10 as the drive source moves and reaches a prescribed position, it is detected by a CW end sensor 11 or a CCW end sensor 12. A CW limit signal 13 or CCW limiting signal 14 is delayed by the delay circuit 5 and inputted into the control circuit 2 via the gate logics 8 or 9 to stop the pulse motor 10. The delay circuit 5 uses a logic such as a shift register and a counter and is constituted of a logic circuit, based on a control clock generated by a transmitting circuit 4, thus it is possible to attain noise reduction. |
