Method and circuit for detecting address limit violations in a microprocessor-based computer

摘要

An address limit violation detection circuit in a microprocessor-based computer system for eliminating delay between the generation of a definite limit violation (DLV) signal and the generation of a potential limit violation signal. The detection circuit includes a full adder circuit which is adapted to receive a linear address, a base address, and a limit value and further adapted to produce a plurality of sum bits and a plurality of carry bits in response thereto. The circuit further includes a DLV detection circuit adapted to receive the plurality of sum bits and carry bits from the full adder circuit and further adapted to produce a DLV signal in response thereto. The DLV signal is indicative of whether the linear address is greater than the sum of the base address and the limit value. The invention further includes a PLV detection circuit adapted to receive the plurality of sum bits and carry bits from the full adder circuit and further adapted to produce a PLV signal in response thereto wherein the PLV signal indicates whether the linear address is equal to the sum of the base address and the limit value. In a presently preferred embodiment, the PLV detection circuit includes n-1 EXOR gates where each of the n-1 EXOR gates receives one bit of the plurality of sum bits and a corresponding bit of the plurality of carry bits as inputs. Each of the n-1 EXOR gates produces an output which comprises one bit of n-bit result.