发明名称 DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
摘要 A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.
申请公布号 US5959321(A) 申请公布日期 1999.09.28
申请号 US19970901876 申请日期 1997.07.29
申请人 LG SEMICON, LTD. 发明人 LEE, CHANG JAE;YANG, WON SUCK;PARK, KONG HEE
分类号 G11C11/34;H01L21/8242;H01L27/108;(IPC1-7):H01L27/108;H01L29/76;H01L29/94;H01L31/119 主分类号 G11C11/34
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