| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the capacitive loads of bit lines to contrive the speedup of the operation of a nonvolatile semiconductor memory by an increase in the capacity of the nonvolatile semiconductor memory and to ensure the prevention of an augmentation in a chip size and the easiness of a patterned layout. SOLUTION: First and second split bit lines BLa0 and BLb0 are arranged to one main bit line BL0 and a memory cell array is split into a plurality of blocks. Selecting transistors Q0 to Q1 and Q4 to Q5 and discharge transistors Q2 to Q3 and Q7 to Q6 are respectively arranged on both sides opposing to each other of the array 11 and moreover, wirings 20 of a prescribed potential ARGND and wirings 21 and 22 of selecting signals DCBLa and DCBLb are arranged. A second gate electrode wiring 23 connects a gate of the first selecting transistor Q0 and a gate of the second discharge transistor (equivalent to the Q3), which is related to the main bit line adjacent to the transistor Q0, with the electrodes 21 and a first gate electrode wiring 25 connects a gate of the second selecting transistor Q1 and a gate of the first discharge transistor Q2 with the electrodes 21.</p> |
