EMBEDDED STATIC RANDOM ACCESS MEMORY FOR FIELD PROGRAMMABLE GATE ARRAY

摘要

A dual ported (simultaneous read/write) SRAM block (12) with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core (10) is disclosed. Each SRAM block (12) contains circuits in both the read port (28) and the write port (26) that permit the SRAM blocks (12) to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector (110) is provided such that when both read and write ports (28, 26) in the SRAM block (12) access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block (12) or the new data being written to the SRAM block (12).