Bit-synchronization circuit for e.g. passive double star PDS system, large-sized computer, optical receiver in e.g. large-scale optical interconnection network, large-capacity ATM switch

摘要

The phase of the phase comparator (3), the input data to the identification circuit (4) and the clock of the identification circuit are equal. The bit-synchronization circuit includes a polyphase clock generator circuit (2) which generates mutually different clocks whose phase is synchronized with the input standard clock. The identification circuit identifies the input data, respectively, using each clock from circuit (2) as a data identification clock. The phase comparator compares the phase of the input data and each clock from circuit (2). A phase determining circuit (5) determines the clock whose level transmission timing is generated in the center section of the level transition timing, at which the input data adjoin mutually, depending on the phase comparison result. A selector (6) chooses and derives the output of the identification circuit, using the clock determined by the phase determining circuit as the data identification clock.