Switch with programmable delay

摘要

A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal to an error control signal derived from an error amplifier or in the alternative to a disable signal. The output of the comparator is latched on until a reset signal is received. The reset signal is produced when the ramp signal is discharged below a predetermined level. The programmable delay circuit is useful in a secondary side post regulator to control a totem pole driver. The totem pole driver in turn controls a switching device coupled to a voltage on a secondary winding.