Sequential permutation apparatus for rearranging input data

摘要

A switching circuit supplies a signal from a write memory selection terminal and its inverted signal to one of a first or a second selector and the other of the first or the second selector according to an output signal from a forward/backward translation selection terminal. In a forward translation process, the first and second selectors select a translated address on a translated address bus in a writing stage and select an input address on an input address bus in a reading stage. In a backward translation process, the selectors select the input address in the writing stage and select the translated address in the reading stage. Consequently, the forward translation and the backward translation are executed using the same translation table. An address translation table memory therefore stores therein only either a translation table for forward translation or a translation table for backward translation.