| 摘要 |
A color signal processing circuit of a camera DSP chip for use with a CCD includes a matrix circuit for converting color signals from the CCD into R-G and B-G signals, a hue/gain controlling circuit for multiplying the R-G signal by a R-hue coefficient and a R-gain coefficient and multiplying the B-G signal by a B-hue coefficient and a B-gain coefficient to form B-Y and R-Y signals by adding the R-G and B-G signals respectively multiplied by respective hue and gain coefficients, a zoom-processing circuit for zoom-processing the B-Y and R-Y signals converted in the hue/gain controlling circuit in a zoom mode, and a frequency converting circuit for synchronizing the B-Y and R-Y signals from the hue/gain controlling circuit or zoom-processed in the zoom-processing circuit with a clock having the frequency four times as large as a color burst signal to provide synchronized signals while loading the color burst signals. Thus, zoom data of the camera DSP chip is reduced by as many as 2 bits without affecting picture quality while decreasing the number of external pins on the DSP chip when the zoom-processing circuit is separate from the DSP chip. The B-Y and R-Y color difference signals are utilized as the zoom data in place of the R-G and B-G signals thereby facilitating the zoom processing and overall operation in the system application level.
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