| 发明名称 |
MEMORY SYSTEM |
| 摘要 |
According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes. |
| 申请公布号 |
US2016179402(A1) |
申请公布日期 |
2016.06.23 |
| 申请号 |
US201514644590 |
申请日期 |
2015.03.11 |
| 申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
IWASHIRO Taro;Haga Takuya |
| 分类号 |
G06F3/06;G06F12/14 |
主分类号 |
G06F3/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory system comprising:
a nonvolatile semiconductor memory including a first chip and a second chip; a bus connected to the first chip and the second chip in common; and a controller that issues a first command to the first chip via the bus, the controller queuing a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command, the controller issuing to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes. |
| 地址 |
Minato-ku JP |
