| 摘要 |
A constant divider is described which includes: a plurality of stages of partial dividers each including a group of decoders, one decoder being provided for each bit of a dividend and each decoder outputting a quotient and remainder resulting from division of a value associated with a bit when that bit is "1", and quotient adders that add the quotient output of each decoder of that decoder group; in partial dividers other than that of the last stage, a remainder adder that adds output values of remainders of each decoder of the decoder group of that stage; in the last stage of the partial dividers, a corrective decoder that outputs a corrective output of the quotient and a corrective output of the remainder produced by dividing the output of the remainders of each decoder of the last-stage decoder group by the divisor; and finally, a quotient output adder that adds the quotient adder output of each stage and the corrective output of the quotient of the last stage, wherein the first-stage partial divider receives the dividend, partial dividers of succeeding stages receive as the dividend the output of the remainder adder of the partial divider of the preceding stage.
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