发明名称 |
Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal |
摘要 |
An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.
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申请公布号 |
US5946268(A) |
申请公布日期 |
1999.08.31 |
申请号 |
US19980012558 |
申请日期 |
1998.01.23 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA;MITSUBISHI ELECTRIC ENGINEERING COMPANY LIMITED |
发明人 |
IWAMOTO, HISASHI;MURAI, YASUMITSU |
分类号 |
G11C11/407;G06F1/06;G11C7/22;H03K5/00;H03K5/13;H03L7/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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