| 摘要 |
The invention provides a clock signal distributing circuit wherein the position at which the buffer section is disposed is determined from the positions and characteristics of the clock signal input section and the load section and the characteristics of the buffer section and the wiring section, and wirings are made through the clock signal input section, one or more stage buffer sections, and the load section, so that the signal transmission delay time as well as the skew of clock signals can be adjusted.
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