| 摘要 |
<p>Transfer procedure in which the controlling microprocessor (10) executes serial data transfer using a clock line (BCL) to control data transfer, along data line (BDA), with cycles of transfer using addressing interspersed with direct transfer cycles. IN each cycle the processor transmits activation impulses when the clock line is at a first logic state. Prior to an address cycle the bits (A3-A0) are transmitted on the data line, with the synchronizing impulses transmitted on the clock line. The peripheral unit (12) receives the initiating bits then accesses memory according to the address transferred for reading or writing data bits (D7-D0). The latter being received in conjunction with the synchronizing clock signal. In a direct access cycle the memory address for access is determined prior the transfer. An Independent claim is made for an interface for carrying out the data transfer procedures.</p> |
