| 摘要 |
A phase synchronous circuit, in the process of locking an internal signal to an input signal by a PLL loop, makes a frequency of the internal signal stepwise approximate to a frequency of the input signal under digital PLL control at a first stage, and adjusting a phase under analog PLL control at a next stage, thus controlling a variable frequency oscillator at the two stages. A gain with which an analog PLL control system is burdened can be thereby reduced, and a gain of VCO may not be set larger than required even if a frequency of an output signal fout is high.
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