发明名称 NONVOLATILE SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To suppress variations in threshold voltages after erasue small by drawing out and erasing electrons stored in a conductive floating-gate while impressing a voltage negative with respect to semiconductor regions on the word line connected to the control gate of a memeory cell into a source region and writing data in it while injecting electrons from the drain region of the memory cell into the floating-gate. SOLUTION: In a negative charge impressing circuit, when an erase signal EP is made to be a low level, after the time determined in a delay circuit is elapsed, a signal EPDLY becomes a low level and a row decoder separating signal SET becomes a high level and a row decoder circuit is electrically separated from a word line. Next, an oscillator OSC2 starts an oscillation and complementary pulses PU1, PU2 are generated and a negative voltage Vppn is generated by the principle of a charge pump. Then, electrons being in a floating-gate is drawn out to be erased by the high voltage between the gate and the source of a memory cell by impressing the negative voltage Vppn on the gate of the memory cell and impressing a positive voltage from an external power source on the source.</p>
申请公布号 JPH11224493(A) 申请公布日期 1999.08.17
申请号 JP19980338776 申请日期 1998.11.30
申请人 HITACHI LTD 发明人 SEKI KOICHI;KUME HITOSHI
分类号 G11C16/04;G11C16/02;G11C16/06;G11C17/00;(IPC1-7):G11C16/04 主分类号 G11C16/04
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