| 摘要 |
A memory speed testing circuit including a memory addressing circuit (11, 13, 15) for sequentially providing to the address input of the memory device a binary address A and a binary address +E,ovs A+EE which is a binary 1's complement of the binary address A, wherein the binary address +E,ovs A+EE is provided within a selected time interval after the provision of the binary address A when the memory device is in a read mode; a data circuit (21, 23, 24) for generating a first binary test word and a second binary test word that is a 1's complement of the first binary test word; wherein the first binary test word is input to the data port of the memory device when the binary address A is provided the address input of the memory device when the memory device is in the write mode, and wherein the second binary test word is input to the data port of the memory device when the binary address +E,ovs A+EE is provided to the address input of the memory device when the memory device is in the write mode; and a comparator (25) for comparing the first binary test word with a memory read output provided by the memory device pursuant to a binary address A, and comparing the second binary test word with a memory read output provided by the memory device pursuant to a binary address +E,ovs A+EE which is a 1's complement of the binary address A.
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