| 摘要 |
PROBLEM TO BE SOLVED: To obtain a clock recovery circuit that has a wride range of an operational clock cycle time and a double frequency function. SOLUTION: A clock recovery circuit of this semiconductor device is made up of a clock input buffer(CIB), a clock divider(CID) that supplies an internal clock, a delay monitor(DMC) connecting to the clock input buffer, a 1st delay circuit group(FDA) connecting to the delay monitor (DMC), a 2nd delay circuit group (BD) connecting to the clock driver (CID), and a control circuit (MCC) that controls the 2nd delay circuit group (BDA) depending on an output of the clock input buffer (CIB) and an output of the 1st delay circuit group (FDA). While a clock cycle number from an external clock to an internal clock is automatically switched in response to the clock cycle time, the external clock is delayed depending on its period to generate the internal clock and a delay time difference of the delay circuits of the delay circuit groups FDA, BDA is made an integer multiple. |
