| 摘要 |
<p>An integrated circuit including a DMA controller (20), an ADC (2-14) having a plurality of conversion channels, and address and data ports (P0,P2) for connection to external memory means (26), the DMA controller (20) being arranged to read a channel id from the memory means (26) using the address and data ports (P0,P2) which channel id is representative of one of the said conversion channels, to pass the read channel id to the ADC (2-14), to cause the ADC to perform an analog-to-digital-conversion on the conversion channel represented by the channel id, to receive the conversion result from the ADC and to write the conversion result back to the memory means using the address and data ports. Also, an integrated circuit including a microcontroller (24) having an output port (P0,P2), an address valid output line (wr,rd), a latch (40,42) coupled to the output port, and a latch control line (ale) coupled to the latch control of the latch, the microcontroller (24) being operable to present a first range of address bits at its output port, to activate the latch control line (ale) to cause the latch to latch the first range of bits, to present a second range of address bits at its output port and to activate the address valid line to indicate that the combination of the first and second ranges present on the latch outputs and the output port respectively, are valid. <IMAGE></p> |
