发明名称 Apparatus and method for performing efficient read and write operations in a multiple bus system
摘要 A bus control apparatus is provided which can control the access timing between a central processing unit and a peripheral equipment without increasing the size and the cost of the entire system. The access timing between the central processing unit and the peripheral equipment is controlled in accordance with an operation timing of the peripheral equipment described in a timing table.
申请公布号 US5935428(A) 申请公布日期 1999.08.10
申请号 US19960707059 申请日期 1996.09.03
申请人 SONY CORPORATION 发明人 YAMAMOTO, YASUYUKI;ISHIBASHI, TOSHIYA
分类号 G06F13/12;G06F13/40;G06F13/42;(IPC1-7):G06F13/00 主分类号 G06F13/12
代理机构 代理人
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