Scan path circuitry including a programmable delay circuit
摘要
A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.
申请公布号
US5936977(A)
申请公布日期
1999.08.10
申请号
US19970932315
申请日期
1997.09.17
申请人
CYPRESS SEMICONDUCTOR CORP.
发明人
CHURCHILL, JONATHAN F.;RAFTERY, NEIL P.;HENDRY, COLIN J.;SHANMUGAM, JEYAKUMAR;FINN, MARK A.;SURRETTE, THOMAS M.;PHELAN, CATHAL G.;PANCHOLY, ASHISH